The phase-locked loop (PLL) circuit is widely used in radio, telecommunications, and other electronic applications. A PLL essentially works to synchronize the output phase and frequency of a controllable oscillator to match the output phase and frequency of a reference oscillator. In this way, a PLL can also be used to synthesize multiple frequencies from a single reference oscillator. Thus, PLLs are often used to generate stable frequencies for use as clocks in other circuits (e.g., analog to digital converters, microprocessors, etc). Since the accuracy and stability of clock signals are essential for proper circuit functionality, it is necessary to design PLLs so that their output signals remain as stable as possible.
FIG. 1 illustrates a simple schematic of a conventional charge-pump PLL. PLL 100 includes a phase detector 102, a charge pump 104, a low pass filter 106, and a voltage-controlled oscillator (VCO) 108. Low pass filter 106 includes resistor 110 and filter capacitor 112.
In operation, phase detector 102 receives reference signal 114 from an external oscillator (not shown). Phase detector 102 compares the phase of reference signal 114 to that of VCO output signal 116. Depending on the phase difference, phase detector 102 then outputs a pulse of specific duration at UP output 118 and also at DOWN output 120. A pulse at UP output 118 causes charge pump 104 to add charge to filter capacitor 112, whereas a pulse at DOWN output 120 causes charge pump 104 to remove charge from filter capacitor 112. As charge is added or removed from filter capacitor 112, the voltage at the input of VCO 106 (Vtune input 122) is thereby increased or decreased. This causes VCO 106 to respond by increasing or decreasing the frequency of VCO output signal 116. The phase of VCO output signal 116 is then again compared to that of reference signal 114, and the cycle repeats again. In this manner, the phase and frequency of VCO output signal 116 is repeatedly adjusted to eventually match that of reference signal 114.
Once the phase and frequency of output signal 116 matches that of reference signal 114, PLL 100 is considered to be in the “locked” state, and mainly functions to maintain a constant voltage at Vtune input 122, such that VCO output signal 116 remains “locked” to that of reference signal 114. This is implemented by phase detector 102 outputting identical pulses on UP output 118 and DOWN output 120, such that no net charge is transferred to filter capacitor 112, thus allowing the voltage at Vtune input 122 to remain constant.
In FIG. 1, only the fundamental components of a typical PLL were shown, for simplicity in the explanation of basic PLL functionality. In practice, PLLs typically implement another important component known as a frequency divider. A frequency divider is a circuit that takes an input signal with frequency, fin, and produces an output signal with frequency fout, where fout=fin/n, and n is an integer. Most PLLs include a divider in the feedback loop, between the VCO output and the feedback input to the phase detector (often referred to as a “feedback divider”). In this manner, the PLL can serve as a frequency synthesizer and produce a range of frequencies from a single fixed reference input (typically a crystal oscillator). Some PLLs also include a divider between the external crystal oscillator and the reference input to the phase detector (often referred to as a “reference divider”).
In many PLL system applications, it is necessary to change the crystal oscillator frequency during operation, while keeping the PLL output constant. An example of this is using the PLL output to provide a fixed sampling clock to an analog-to-digital converter (ADC) digitizing an audio signal, and dynamically changing the crystal oscillator frequency from a low frequency to a high frequency (and vice versa). This can occur in a multi-standard cell phone with a low frequency clock for low power operation, where dynamic switching between low and high frequency asynchronous clocks would constantly be occurring in order to minimize power consumption. Changing the crystal oscillator frequency also requires changing the divider ratios to keep the PLL output frequency constant. Therefore, in dynamic switching, it is necessary to hold the present VCO frequency, wait a period of time, change the crystal oscillator, change the divider data, and then relock the VCO frequency to the same frequency before the hold state. However, after a hold and wait period, large phase errors typically arise that cause a large temporary frequency glitch in the PLL output upon relock, which is undesirable. Therefore it is desired to implement “zero phase start” (ZPS) initialization of the PLL, in which the phase error upon relock is minimized, such that the PLL output remains as stable as possible. Conventional techniques on implementing ZPS in PLL initialization will be discussed below.
FIG. 2 illustrates a conventional charge pump PLL system 200, which implements ZPS upon PLL initialization. As illustrated in the figure, PLL system 200 includes a reference divider 204, a phase detector 206, a charge pump 208, a VCO 210, a feedback divider 212, a data storage and state machine portion 214 and a low-pass filter 228.
Low-pass filter 228 includes a storage capacitor 230, compensation capacitor 234 and a resistor 232. Low-pass filter 228, resistor 232 and storage capacitor 230 construct a RC circuit 236 that passes low frequency signals but attenuates undesired high frequency signals, wherein compensation capacitor 234 compensates for the phase shift caused by RC circuit 236. Low-pass filter 228 smoothes Vtune signal 222 by removing short-term high-frequency oscillations (typically noise) that are passed through charge pump 208.
Reference divider 204 is arranged to receive a reference signal 202 as input and output a divided reference signal 218. Phase detector 206 is arranged to receive divided reference signal 218 and divided feedback signal 220 as input and output a UP signal 224 and a DOWN signal 226. Charge pump 208 is arranged to receive UP signal 224 and DOWN signal 226 from phase detector 206 and to output signal 222 to VCO 210 and to low-pass filter 228. VCO 210 provides an output signal 216 to an application circuit (not shown) and to feedback divider 212. Feedback divider 212 receives output signal 216 and provides divided feedback signal 220 to phase detector 206.
In operation, reference divider 204 receives reference signal 202 from an external crystal oscillator (not shown). Reference divider 204 produces a divided reference signal 218, which has the frequency of reference signal 202 divided by an integer ratio M. Phase detector 206 receives divided reference signal 218 from reference divider 204 and divided feedback signal 220 from feedback divider 212. Phase detector 206 measures the phase difference between divided reference signal 218 and divided feedback signal 220 and outputs UP signal 224 and DOWN signal 226 accordingly. UP signal 224 and DOWN signal 226 each consist of a pulse, with a pulse width depending on the measured phase difference. If there is a leading phase difference (divided reference signal 218 leads divided feedback signal 220), then UP signal 224 consists of a pulse having pulse width larger than that of DOWN signal 226. If there is a lagging phase difference (divided reference signal 218 lags divided feedback signal 220), then DOWN signal 226 consists of a pulse that is longer duration than that of UP signal 224.
Charge pump 208 receives UP signal 224 and DOWN signal 226, and depending on their relative pulse durations, either pumps or removes charge from storage capacitor 230, which effectively increases or decreases the voltage at Vtune 222. VCO 210 responds to the change in Vtune 222 by either increasing or decreasing the frequency of output signal 216. Output signal 216 is input into feedback divider 212, which produces a divided feedback signal 220, which has the frequency of feedback signal 216 divided by an integer ratio N. Divided feedback signal 220 is then input back into phase detector 204, and the process repeats again. In this manner, PLL system 200 functions to enable VCO 210 to output a stable output signal 216 to an application circuit (not shown), such that the frequency and phase of divided reference signal 218 and divided feedback signal 220 are the same, or as close as possible.
Once the phase and frequency of divided feedback signal 220 matches that of divided reference signal 218, PLL system 200 is considered to be in the “locked” state, and mainly functions to maintain a constant voltage at Vtune input 222, such that divided feedback signal 220 remains “locked” to that of divided reference signal 218. This is implemented by phase detector 206 outputting UP signal 224 and DOWN signal 226 that consist of identical pulses, such that no net charge is transferred to storage capacitor 230, thus allowing the voltage at Vtune input 222 to remain constant.
Data storage and state machine portion 214 is what determines the state of PLL system 200 (hold, relock, etc). Data storage and state machine portion 214 includes a look-up table (LUT) having a current/desired state functions in addition to corresponding flip-flop data. More specifically, the LUT is preprogrammed such that desired state may be quickly determined for any detected state, i.e., a current state. Further, once the current state is detected, and therefore the desired state is determined, the corresponding data required to change the logic of flip-flops to affect the desired state is additionally quickly determined by the LUT.
Data storage and state machine portion 214 is operable to detect a current state of reference divider 204, i.e., the state of flip-flops (not shown) within reference divider 204, which provides divided reference signal 218 as a function of reference signal 202. Further, data storage and state machine portion 214 is operable to provide new data to reference divider 204 in order to change the state of the flip-flops within reference divider 204, which will therefore change divided reference signal 218 as a function of reference signal 202. Similarly, data storage and state machine portion 214 is operable to detect a current state of feedback divider 212, i.e., the state of flip-flops (not shown) within feedback divider 212, which provides divided feedback signal 220 as a function of output signal 216. Further, data storage and state machine portion 214 is operable to provide new data to feedback divider 212 in order to change the state of the flip-flops within feedback divider 212, which will therefore change divided feedback signal 220 as a function of output signal 216. In this manner, the divide ratio M for reference divider 204 and the divide ratio N for feedback divider 212 are determined by data storage and state machine portion 214.
As previously mentioned, PLL 200 implements ZPS in order to minimize phase error upon initialization. The theory behind ZPS is explained further with regards to FIG. 3.
FIG. 3 shows timing diagrams illustrating examples of each of the three possible scenarios detected by phase detectors when measuring phase differences: positive phase difference, zero phase difference, and negative phase difference. To illustrate an example of each case, FIG. 3 includes a top waveform 302, a middle waveform 304, and a bottom waveform 306. These graphs are generic and can be discussed in terms of any charge-pump PLL, but for ease of explanation, we explain FIG. 3 in terms of PLL 200 of FIG. 2.
In top waveform 302, x-axis 308 represents time, whereas y-axis 310 represents current into storage capacitor 230. In this case, the rising edge of divided feedback signal 220 (indicated by time point 312) is ahead of the rising edge of divided reference signal 218 (indicated by time point 314), thus indicating a positive phase difference. This causes the pulse on DOWN signal 226 to be of longer duration than the pulse on UP signal 224. Thus, as shown in the figure, the current going out of storage capacitor 230 (current 316, denoted by iD) is on for longer time than that of the current going into storage capacitor 230 (current 318, denoted by iU). As a result, the charge removed from storage capacitor 230 (charge 320, denoted by QD) is larger than the charge pumped into capacitor 230 (charge 322, denoted by QU), and the net charge into capacitor 230 (QU−QD) is negative. This causes the voltage at Vtune 222 to decrease, which in turn reduces the frequency of output signal 216, such that divided feedback signal 220 slows clown to become more in phase with divided reference signal 218.
In middle waveform 304, x-axis 324 represents time, whereas y-axis 308 represents current into storage capacitor 230. In this case, the rising edge of divided feedback signal 220 (indicated by time point 314) coincides with the rising edge of divided reference signal 218, thus indicating zero phase difference. This causes the pulse on DOWN signal 226 to be of same duration as the pulse on UP signal 224. Thus, as shown in the figure, there is current going out of storage capacitor 230 (current 328, denoted by iD) and current going in to storage capacitor 230 (current 326, denoted by iU) for the same amount of time. This causes the net charge pumped into storage capacitor 230 (charge 330, denoted by QD) to be identical to the charge removed from storage capacitor 230 (charge 332, denoted by QD). Hence there is no change to the voltage on Vtune 222, and output signal 216 remains constant.
In bottom waveform 306, x-axis 334 represents time, whereas y-axis 308 represents current into storage capacitor 230. In this case, the rising edge of divided feedback signal 220 (indicated by time point 336) lags behind the rising edge of divided reference signal 218 (indicated by time point 314), thus indicating a negative phase difference. This causes the pulse on UP signal 224 to be of longer duration than the pulse on DOWN signal 226. Thus, as shown in the figure, the current going out of storage capacitor 230 (current 340, denoted by iD) is on for shorter time than that of the current going into storage capacitor 230 (current 338, denoted by iU). As a result, the charge pumped into storage capacitor 230 (charge 342, denoted by QU) is larger than the charge removed from storage capacitor 230 (charge 344, denoted by QD), and the net charge into capacitor 230 (QU−QD) is positive. This causes the voltage at Vtune 222 to increase, which in turn increases the frequency of output signal 216, such that divided feedback signal 220 speeds up to become more in phase with divided reference signal 218.
When PLL 200 is in lock, the rising edge from divided feedback signal 220 lines up with the rising edge of reference signal 218, and no net charge goes into storage capacitor 230, as shown in middle waveform 304. In this manner, the voltage on Vtune 222 remains constant and output signal 216 remains constant. As mentioned previously, in many PLL system applications, during the lock condition it is often desired to hold the present output frequency, wait a period of time, and then relock the output frequency to the same frequency before the wait period. Thus, upon relocking PLL 200 after a hold period, it is desired to initialize with the rising edges of divided feedback signal 220 and divided reference signal 218 already lined up (zero phase difference), such that no net charge is transferred onto storage capacitor 230 and output signal 216 remains unperturbed. This is the motivation behind the implementation of ZPS in PLL systems.
The hold and relock sequences are implemented in PLL system 200 as follows. While PLL system 200 is in the locked state, if the hold command is issued from logic within data storage and machine portion 214, the addresses of reference divider 204 and feedback divider 212 are stored in the LUT of data storage and machine portion 214. The reference divider ratio M and the feedback divider ratio N are also stored in data storage machine portion 214. During the hold period, the frequency of the crystal oscillator (not shown) can be changed. If the crystal oscillator frequency is changed, however, a new reference divider ratio M and a new feedback divider ratio N must be calculated such that output frequency 216 remains constant. Also, the new addresses to be put into flip-flops (not shown) in each of reference divider 204 and feedback divider 212 must be calculated such that upon relock, the positive edge of divided reference signal 218 lines up with the positive edge of divided feedback signal 220 going into phase detector 206. This provides for a ZPS upon relocking PLL system 200, so that phase error and glitches in output signal 216 are minimized.
This conventional implementation of ZPS is not ideal however, since it requires complicated calculations of the new addresses to be put into reference divider 204 and feedback divider 212. These calculations takes up a significant amount of time, not to mention extra power and space due to the additional logic and circuitry required.
Another problem of PLL system 200 is the leakage of charge during the hold state. When the hold command is executed, charge pump 208 needs to keep the voltage at Vtune 222 constant so that the frequency and phase of output signal 216 remain unchanged during the hold period. However, the output of charge pump 208 is usually a drain terminal of a CMOS transistor, which has high leakage current. As a consequence, during the hold state there is significant charge leakage off storage capacitor 230, which alters the voltage on Vtune 222 and thus causes changes in the frequency and phase of output signal 216.
A second type of conventional PLL system implementing ZPS will now be described with reference to FIG. 4.
FIG. 4 illustrates another conventional PLL system 400, which uses a charge pump with a coarse tune digital-to-analog converter (DAC). As illustrated in the figure, PLL system 400 includes a reference divider 404, a phase detector 406, a charge pump 408, a low pass filter 410, a VCO 412, a time-to-digital converter 414, an up/down integrating counter 416, a DAC 418, a data storage and state machine portion 420 and a feedback divider 422.
Reference divider 404 is arranged to receive a reference signal 402 as input and to output a divided reference signal 424. Phase detector 406 is arranged to receive divided reference signal 424 and a divided feedback signal 442 as input and to output a phase error signal 426 to charge pump 408 and time-to-digital converter 414. Charge pump 408 is arranged to receive phase error signal 426 as input and to output a fine tuning signal 428 to VCO 412. Time-to-digital converter 414 is arranged to receive phase error signal 426 as input and to output a signal 430 to up/down integrating counter 416. Up/down integrating counter 416 is operable to output a signal 432 to DAC 418. DAC 418 is arranged to receive signal 432 and output a coarse tuning signal 434. VCO 412 is arranged to receive fine tuning signal 428 and coarse tuning signal 434 as inputs and to output an output signal 436 to an application circuit (not shown) and to feedback divider 422. Feedback divider 422 is arranged to receive output signal 436 as input and provide divided feedback signal 442 to phase detector 406. Data and state machine portion 420 updates data for each of reference divider 404, feedback divider 422, and DAC 418 via data buses 444, 440, and 448, respectively.
Similar to low pass filter 228 discussed above with reference to FIG. 2, low-pass filter 410 removes unwanted high-frequency signals (typically noise) from fine tune signal 428 before fine tune signal 428 is provided to VCO 412.
PLL system 400 operates in a very similar manner as PLL system 200 of FIG. 2. PLL system 400 functions to enable VCO 412 to output a stable output signal 436 to an application circuit (not shown), such that the frequency and phase of divided reference signal 424 and divided feedback signal 442 are the same, or as close as possible.
PLL system 400 differs from PLL system 200 of FIG. 2 in that there are two branches for controlling VCO 412, a coarse tuning branch, which includes time-to-digital converter 414, UP/DOWN integrating counter 416, and DAC 418, and a fine tuning branch, which includes charge pump 408 and low pass filter 410. In operation, VCO 412 is first adjusted by coarse tune signal 434 until the frequency of output signal 336 is close to the desired value, e.g., such that the phase error signal 426 is within a predetermined value. VCO 412 is then adjusted via fine tuning signal 428 to get make output signal 436 more accurate.
Similar to data storage and state machine portion 214 discussed above with reference to FIG. 2, data storage and state machine portion 420 includes a LUT having a current/desired state functions in addition to corresponding flip-flop data. Data storage and state machine portion 420 is operable to detect the current states of reference divider 404 and feedback divider 422, and to also provide new data to change the state of flip-flops (not shown) within reference divider 404 and feedback divider 422.
Data storage and state machine portion 420 differs from data storage and state machine portion 214 of FIG. 2, in that data storage and state machine portion 420 additionally provides data to DAC 418, via data bus 438, in order to change coarse tuning signal 434 as a function of signal 432.
As mentioned previously, in many PLL system applications, during the lock condition it is often desired to hold the present output frequency, wait a period of time, and then relock the output frequency to the same frequency before the wait period. In PLL system 400, this is implemented in a similar fashion as in PLL system 200 of FIG. 2. While PLL system 400 is in the locked state, if the hold command is issued from logic within data storage and machine portion 420, the addresses of reference divider 404 and feedback divider 422 are stored in the LUT of data storage and machine portion 420. The reference divider ratio M and the feedback divider ratio N are also stored in data storage machine portion 420. During the hold period, the frequency of the crystal oscillator (not shown) can be changed. If the crystal oscillator frequency is changed, however, a new reference divider ratio M and a new feedback divider ratio N must be calculated such that output frequency 436 remains constant. Also, the new addresses to be put into flip-flops (not shown) in each of reference divider 404 and feedback divider 422 must be calculated such that upon relock, the positive edge of divided reference signal 424 lines up with the positive edge of divided feedback signal 442 going into phase detector 406. This provides for a ZPS upon relocking PLL system 300, so that phase error and glitches in output signal 436 are minimized.
Since it employs coarse and fine tuning capabilities, the conventional PLL system 400 of FIG. 4 has improved performance and accuracy in maintaining a stable output. However, the ZPS still has the issue of needing to calculate the values of the new data to be loaded into flip-flops of the reference divider 404 and feedback divider 422 upon relocking. As discussed previously, these calculations not only require time but additional power, circuitry, and space. Moreover, during the hold state, the charge leakage from storage capacitor 446 is still a problem, which affects the stability of output signal 336.
These issues pose a problem because in many PLL applications, system designers would like to switch between a low and high frequency crystal oscillator clock, while keeping the PLL output frequency constant. This dynamic switching of the reference frequency requires the PLL to enter the hold state while the reference clock is changed. During this time, charge leakage will cause the output frequency to drift. Also, upon relock, ZPS must be implemented to reduce phase error. However, the conventional implementation of ZPS takes up time and resources due to the calculations involved.
Due to these drawbacks, conventional PLL systems have poor performance when dynamically switching between high frequency and low frequency reference input clocks. Even if ZPS is implemented to reduce phase error upon relock, the extra logic & circuitry required consumes power, uses up space and increases the response time of the PLL. In addition, charge leakage during hold state causes changes in the frequency of the output signal, which is undesirable.
What is needed is a PLL system that can minimize changes in its output frequency during the hold state and also implement ZPS upon initialization (relock), in a manner that does not require a significant amount of additional calculations, power consumption, and silicon space.